A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs

Published in In the proceedings of 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020

Recommended citation: Abhishek Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde, "A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs." In the proceedings of 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020. (https://people.ece.ubc.ca/hosseino/publications/SpMV_FPL2020_published.pdf)