High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay

Published in In the proceedings of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020

Recommended citation: Xiangwei Li, Kizheppatt Vipin, Douglas Maskell, Suhaib Fahmy, Abhishek Jain, "High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay." In the proceedings of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020. (http://wrap.warwick.ac.uk/132228/7/WRAP-high-throughput-accelerator-framework-linear-Fahmy-2020.pdf)