Publications

“Entropy Maximization in Sparse Matrix by Vector Multiplication”[PDF]
Paolo D’Alberto, Abhishek Kumar Jain, Ismail Bustany, Henri Fraisse, Mansimran Benipal, and Dinesh Gaitonde
SIAM Conference on Computational Science and Engineering (CSE), March 2021.

“High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay”[PDF]
Xiangwei Li, Kizheppatt Vipin, Douglas L Maskell, Suhaib A Fahmy, and Abhishek Kumar Jain
International Symposium on Circuits and Systems (ISCAS), October 2020.

“Run-time Reconfiguration of NoC in Xilinx ACAP Architecture”[PDF]
Aman Gupta, Sagheer Ahmed, Abhishek Kumar Jain, Ygal Arbel, Abbas Morshed, and David Schultz
International Workshop on Network on Chip Architectures (NOCARC), October 2020.

“Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (Invited)”
Abhishek Kumar Jain
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), October 2020.

“A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs”[PDF][Video]
Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde
IEEE International Conference on Field-Programmable Logic and Applications (FPL), August 2020.

“Performance Assessment of Emerging Memories Through FPGA Emulation”[PDF]
Abhishek Kumar Jain, Scott Lloyd, and Maya Gokhale
Special Issue on Emerging Memory Technologies, IEEE Micro, Jan 2019.

“Microscope on Memory: MPSoC-enabled Computer Memory System Assessments”[PDF][Slides]
Abhishek Kumar Jain, Scott Lloyd, and Maya Gokhale
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, May 2018.

“A Time-Multiplexed FPGA Overlay with Linear Interconnect”[PDF][Slides]
Xiangwei Li, Abhishek Kumar Jain, Douglas L Maskell, and Suhaib A Fahmy
Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, March 2018.

“Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq”[PDF][Slides]
Abhishek Kumar Jain, Xiangwei Li, Suhaib A Fahmy, and Douglas L Maskell
ACM SIGARCH Computer Architecture News (CAN), 43(4):28–33, September 2016.

“Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?”[PDF][Slides]
Abhishek Kumar Jain, Douglas L Maskell, and Suhaib A Fahmy
IEEE International Conference on Pervasive Intelligence and Computing, Auckland, New Zealand, August 2016.

“DeCO: A DSP Block Based FPGA Accelerator Overlay With Low Overhead Interconnect”[PDF][Slides]
Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L Maskell, and Suhaib A Fahmy
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, USA, May 2016.

“Throughput Oriented FPGA Overlays Using DSP Blocks”[PDF][Slides]
Abhishek Kumar Jain, Douglas L Maskell, and Suhaib A Fahmy
Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, March 2016.

“Efficient Overlay Architecture Based on DSP Blocks”[PDF][Slides]
Abhishek Kumar Jain, Suhaib A Fahmy, and Douglas L Maskell
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, Canada, May 2015.

“Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform”[PDF]
Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A Fahmy, and Douglas L Maskell
Journal of Signal Processing Systems (JSPS), vol. 77, no. 1-2, pp. 61–76, October 2014, Springer.

“Microkernel Hypervisor for a Hybrid ARM-FPGA Platform”[PDF][Slides]
Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A Fahmy, and Douglas L Maskell
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013.